This invention relates to first-in/first-out (“FIFO”) memories, and more particularly to implementing such memories using shift registers, for example, in a programmable logic device.
FIFO memories can be used to help transfer data between two different clock regimes that may not be synchronized with one another. For example, data may be received in synchronism with a so-called “write clock” and may require further processing in the order received but in synchronism with a so-called “read clock” which is different from and perhaps not even synchronized with the write clock. A FIFO memory may therefore be used as a data buffer between the circuitry associated with the write clock and the circuitry associated with the read clock. The FIFO memory takes in data in synchronism with the write clock, and the currently oldest data is read out in synchronism with the read clock.
Generally, a FIFO memory must be equipped with circuitry to detect full and empty conditions of the memory. When the memory is full, writing must be stopped (e.g., to prevent loss of data). When the memory is empty, reading must be stopped (e.g., to prevent the reading circuitry from erroneously operating on null data). Full and empty conditions can be detected by counting read and write clock pulses and comparing (e.g., subtracting) those counts. If the write clock pulse count exceeds the read clock pulse count by an amount equal to the capacity of the FIFO memory, the memory is full and further writing should be stopped. If the read clock pulse count is equal to the write clock pulse count, the FIFO memory is empty and further reading should be stopped. Of course writing or reading can be resumed as soon as the FIFO memory is no longer full or empty.
When the read and write clocks are not synchronized with one another, the counts of read and write clock pulses are also not synchronized with one another and it can be difficult to reliably detect full and empty conditions by comparing those counts.